Manufacturing process of semiconductor devices

ABSTRACT

Process of manufacturing semiconductor devices by providing on the surface of a substrate of one conductivity at first only a covering with a doping agent of the other conductivity and then, after the building of mesas, the PN-junction is formed by diffusion in an oxidizing atmosphere whereby simultaneously a protecting SiO 2  layer is formed on the free surface of the mesa.

BACKGROUND OF THE INVENTION

The present invention relates to a process of manufacturingsemiconductor devices, and more particularly to the method ofmanufacturing an isolated PN junction of a semiconductor mesa diode.

The manufacture of diodes by employing the conventional planar process,especially the contacting and encapsulating, is entailed by difficultieswhich are due to the PN-junction positioned on the surface. ThisPN-junction is protected by an SiO₂ -layer, but owing to pressuresexerted during the encapsulation, cracks are likely to result in theSiO₂ -layer so that reverse currents are likely to develop.

As is known, a considerable disadvantage of the planar process is seenin the forming of bent diffusion fronts at the masking edges. It isknown that this is not the case with the mesa process, but instead themesa process is known to have other disadvantages, such as that thedevices produced thereby have a non-protected PN-junction, and that thepassivation is entailed by difficulties in the case of genuine mesadevices.

The German published patent application (DT-OS) No. 24 42 398 disclosesa process of manufacturing a plurality of mesa semiconductor devices inwhich one side of a semiconductor substrate is provided on its entiresurface with a PN-junction area which then, by employing aphotolithographic etching process, is divided into mesas in accordancewith the number of semiconductor devices, whereupon the substratesurface containing the mesas is provided with an oxidation layer. Inthis conventional process, the substrate is first readily diffused andthe covering masking is applied after the mesas have been etched out.The position of the PN-junction and its angle in relation to the mesasurface is determined in this process, above all by the etching depth,with it being naturally difficult to reach the ideal value of 90° forthe angle.

Considering that the masking is effected by thermal oxidation, thediffusion-out at the PN-junction lying at the edge of the mesas maycause a surface depletion at the marginal area. In consequence of this,it may happen that the angle already deviating from the ideal value isstill changed more strongly. This increases the danger of a break-downof the loading of the diode.

SUMMARY OF THE INVENTION

Accordingly, it is the object of the invention to provide a process formanufacturing semiconductor devices not having the aforementioneddisadvantages.

The present invention relates to a process in which on the surface ofthe semiconductor substrate of one conductivity type there is first onlyprovided a coating with a doping agent resulting in the surface layerbeing of the other conductivity type, with the defining of thePN-junction being carried out by way of diffusion following thephotolithographic process and the building of the mesas. A SiO₂ -layeris produced simultaneously by way of thermal oxidation by working in anoxidizing atmosphere while the doping agent is diffused-in at the edgesof the mesas. From this there will result a device which may be referredto as a quasi-mesa device combining the advantages of the electricalproperties of a mesa device with the advantages of the planartechnology. It is of particular advantage that the passivation in theprocess according to the invention is carried out with a thermallyformed oxide which is produced in one step of the process together withthe diffusion.

The devices manufactured in accordance with the process of the inventionshow to have a number of advantages. Thus, for example, it is possibleto achieve high inverse voltages, and by utilizing the entire surface,it is possible to achieve a high current-carrying capacity, and thedevices are insensitive to peak voltages, so that no destruction willoccur during operation as a result of breakdown.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 are sectional views taken through a semiconductor substrateduring successive process steps according to the method of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be explained in detail with reference to anexample of embodiment shown in the accompanying drawings, in whichsilicon nitride is used as the diffusion masking.

Following the usual cleaning process, the surface of the n-conductivesilicon substrate 1 is coated throughout the entire surface with adoping agent, such as boron, resulting in a p-conductive surface layer 2(FIG. 1). Both the temperature and the time of deposition depend on thelater practical application of the devices to be manufactured. Thedoping is carried out in accordance with one of the conventionalprocesses, such as by using boron nitride planar diffusion sources, orwith the aid of PH₃. A coating with the aid of the hydrogen injectionprocess is likewise possible.

As a next step there is carried out, in accordance with FIG. 2, thedeposition of a layer 3 of Si₃ N₄ on the doped substrate 1, whereuponthe layer 3 is covered with a SiO₂ -layer 4. The latter serves as amasking for the Si₃ N₄ -layer 3 lying therebeneath, so that it ispossible to work with phosphoric acid as the etching agent.

In the course of the next step of the process, the etching pattern isproduced with the aid of the photolithographic process. The SiO₂ -layeris first removed with the aid of a photomask, at those points where thesilicon nitride layer 3 and, consequently, the p-doped substrate surfaceis to be exposed. The etching of the silicon dioxide masking is carriedout with the conventional etching solutions, and the removal of thesilicon nitride at the exposed points is carried out with the aid ofphosphoric acid. The finished step of the process is shown in FIG. 3.

As a next step there is effected the structure etching of the siliconsubstrate material, with the silicon nitride layer 3 serving as theetching mask. In so doing, there is utilized the different reactivity ofthe etching solution with silicon and silicon nitride. Depending on whattype of diode is desired, i.e. low-blocking, medium-blocking orhigh-blocking diodes, the depth of the etching groups can be controlledby employing three different etching times.

FIG. 4 shows the completed step of the process, and it is recognizablethat in the course of the etching process there has also been removedthe SiO₂ -layer 4 as positioned over the silicon nitride layer 3. Thegeometry of the future device is now laid down, and the outlined mesastructure thereof becomes distinguishable.

In the course of the hitherto performed process steps, the depth of thePN-junction 2' has not yet been fixed. This is carried out now in thefollowing step, with the doped surface layer 2 as deposited in thecourse of the first step of the process, serving as a source. Thediffusion is carried out in an oxidizing atmosohere, so thatsimultaneously, besides diffusing-in the doping agent, the oxide layer 5as resulting at the edges of the mesa, will prevent a diffusion-out ofthe doping atoms. In the course of this, there results an almost flatdiffusion front, and the angle in relation to the surface at thePN-junction 2' is close to the ideal value; even in the case of arelatively small diffusion depth, there will be obtained an almostrectangular profile (FIG. 5).

In the course of the last step of the process (FIG. 6), and subsequentlyto the removal of the silicon nitride layer 3 by way of etching out,there is produced an electric contact by evaporating various thin metallayers. In the course of this, there is first deposited a thin layer oftitanium 6 over which there is then evaporated the silver layer 7. Thisstep of the process is followed by a photoprocess with the aid of whichthere is enabled the growing of the contacts 8 on the mesa and surfacesin the contact bath. Prior to cutting (breaking) the semiconductorsubstrate into the individual devices, the titanium-silver layer isetched away between the contact surfaces.

In the present example of embodiment the etching of the Si₃ N₄ -layerwas carried out with the aid of phosphoric acid, so that a SiO₂ -layerwas required as an etching mask. In cases where the work is carried outin accordance with the plasma etching process, the SiO₂ -layer may beomitted, and the photoresist layer is deposited directly over the Si₃ N₄-layer.

While we have described above the principles of our invention inconnection with specific apparatus it is to be clearly understood thatthis description is made only by way of example and not as a limitationto the scope of our invention as set forth in the objects thereof and inthe accompanying claims.

We claim:
 1. A method of manufacturing a semiconductor device comprising the steps of:coating to one conductivity type by means of a doping agent the surface layer of a semiconductor substrate of the other conductivity type whereby a PN-junction is formed; forming a mesa structure from said substrate; and diffusing in said doping agent so as to fix the depth of the PN-junction within the semiconductor substrate while simultaneously passivating said mesa structure.
 2. The method of claim 1 wherein passivating said mesa comprises forming an oxide layer thereon by thermal oxidation.
 3. The method of claim 1 or 2 wherein said forming said mesa structure comprises etching said substrate through a patterned mask formed on said surface layer.
 4. The method of claim 1 or 2 further including forming a contact on the surface layer of said mesa structure.
 5. The method of claim 1 or 2 wherein said semiconductor substrate comprises a P-type conductivity.
 6. A method of manufacturing a semiconductor diode comprising the steps of:coating to one conductivity type by means of a doping agent the surface layer of a semiconductor substrate of the other conductivity type whereby a PN-junction is formed; etching said substrate to produce a mesa; and diffusing said doping agent into said mesa to fix the depth of the PN-junction therein while simultaneously forming an oxide layer on said mesa thereby preventing out-diffusion of said doping agent by carrying out said diffusing in an oxidizing atmosphere.
 7. The method of claim 6 wherein said doping agent comprises an N-type dopant.
 8. The method of claim 6 or 7 wherein doping said surface layer comprises doping the entire surface layer with said doping agent. 